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Taking place in San Francisco from Monday through yesterday evening was the RISC-V Summit for discussions around this dominant open-source processor ISA. For those that did not make it to the event, many of the slide decks are available.

The 2021 RISC-V Summit covered the XiangShan as an open-source high performance RISC-V processor out of China, various RISC-V demonstrations, various IoT / edge computing talks in the context of using RISC-V, various Linux kernel features for this ISA, different RISC-V extensions, the various wares of leading RISC-V designer SiFive, and much more.

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