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RISC-V vector instructions support in Renode | Antmicro

By December 9, 2021December 10th, 2021No Comments

Building on top of the flexibility that was the original premise of Renode, our open source simulation framework has for some years now been used for pre-silicon development, architectural exploration and hardware-software co-design.

Using Renode for these kinds of use cases is especially popular in companies who have been encouraged by the open RISC-V ISA to look for new, more software-driven approaches to developing new silicon, especially in the area of machine learning where much of the innovation is being driven by new software breakthroughs, and hardware races to keep up.

RISC-V has been a major focus for Antmicro many years now, as hinted at by Antmicro becoming Founding member of the RISC-V International (then Foundation) in 2015.
Besides SoC implementationstoolssoftware and other open source IP projects that RISC-V has been a steady source of for us, Renode was obviously bound to get RISC-V support sooner rather than later.

Read the full article. 

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