Skip to main content

Prior to spinning out of Galois, engineers from Niobium Microsystems completed work on the 21st Century Cryptography DARPA project. This project developed a proof-of-concept ASIC containing high-performance, low-energy, side-channel resistant implementations of AES-256 cryptographic primitives. These implementations were developed in correct-by-construction fashion, by directly translating formal models of the cryptographic constructs into a hardware implementation language, and realized using asynchronous design to enable a novel side-channel resistance technique in addition to providing performance and energy benefits.

The resulting ASIC, fabricated in the Global Foundries 12nm FinFET process (12LP), includes multiple synchronous and asynchronous cryptographic blocks implementing the AES-256, cryptographic primitive, as well as a RISC-V core (for control and testing of the cryptographic blocks). It incorporates a new side-channel resistance approach called island-based random dynamic voltage scaling (iRDVS) that uses multiple random voltages to hide data-dependent power consumption. This technique was developed and implemented in silicon for the first time during this project.

Read the full article. 

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.