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ASIC roundup of open source RISC-V CPU cores | Oguz Meteer, BitlogIT

By January 18, 2022January 25th, 2022No Comments

While waiting for simulation results for my final paper, I thought I’d synthesize and do place & route of several open source RISC-V CPU cores for fun. Some basic information:

  • All CPU cores were synthesized using a well known 65 nm PDK.
  • Synopsys Design Compiler with ultra effort was used for synthesis.
  • Cadence Innovus was used for place & route.
  • A standard I/O template was generated with Innovus with a square floorplan. This means that the area is most likely not used efficiently which will affect the utilization and maximum clock frequency.
  • Only the CPU core with the register file and a standardized bus (Wishbone, AXI, AHB, etc.) was taken into account. No full SoCs were used to make the comparisons more fair.
  • The goal was maximum clock frequency.

These results are just for fun and to give a very rough estimation of what could be achieved when implemented as an ASIC. There is no SoC, no interconnect, no SRAM, no off-chip memories, etc. so take these results with a mountain of salt. Still, I think it is interesting to see how cores meant to run primarily on FPGAs map onto an ASIC.

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