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RISC-V security IP for chiplet die-to-die communication | Nick Flaherty, EE News Europe

By January 26, 2022January 31st, 2022No Comments

Ceva’s Fortrix RISC-V-based SecureD2D IP enables secure authentication and firmware boot/code load between chiplets in a heterogeneous system-on-chip.

Ceva has launched security IP that protects the communication between separate chiplets used in a heterogeneous system-on-chip design.

The Fortrix SecureD2D, developed by Ceva subsidiary Inrinsix, provides secure authentication and firmware boot/code load between chiplets, which are increasingly used to build complex SoC devices.

The IP consists of a RISC-V controller communicating over a secure bus fabric to hardware-based crypto accelerators which perform rapid encryption and decryption to enable cryptographic functions such as ECDSA, SHA2, AES, and others. SRAM and DMA controllers, a low-level firmware API and a customizable high-level application are also part of the IP package to allow rapid integration into secure chiplets. The IP implements both leader and follower termination points to secure chiplet die that can originate from different vendors and different global supply chains. RISC-V is increasingly popular for security IP with a range of standardized cryptographic instruction extensions.

Read the full article. 

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