The latest ImperasDV test suite for PMP covers the full envelope of configuration options.
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced the beta release of the ImperasDV architectural validation test suites for RISC-V Physical Memory Protection (PMP). The open standard ISA (Instruction Set Architecture) of RISC-V offers developers a wide range of standard extensions and options that support the design of an optimized processor while leveraging the ecosystem of compatibility. The RISC-V Privileged Specification includes PMP as a fundamental approach to memory protection that is essential in security applications that depend on TEE (Trusted Execution Environments) such as Keystone, OpenTitan, and many other leading techniques for security protection. Thus, functional verification of PMP is essential for any RISC-V processor targeted at security applications.