Imperas and Breker partner for Risc-V system-level verification | Steve Bush, Electronics Weekly

By RISC-V Community NewsJuly 7, 2022July 18th, 2022No Comments

RISC-V simulation company Imperas Software has announced a partnership with Breker Verification Systems, a provider of test content synthesis for verification environments, to develop interfaces and standards to unify functional verification design flows.

Read the full article.

Previous PostRISC-V Opens the Door on 48-bit Computing | Agam Shah, HPC Wire
Next PostFirst RISC-V-Based SoC FPGA Enters Mass Production | Microchip Technology, EE Time Asia

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.

Imperas and Breker partner for Risc-V system-level verification | Steve Bush, Electronics Weekly

Previous PostRISC-V Opens the Door on 48-bit Computing | Agam Shah, HPC Wire

Next PostFirst RISC-V-Based SoC FPGA Enters Mass Production | Microchip Technology, EE Time Asia

Stay Connected With RISC-V