Skip to main content
In the News

Imperas Announces Partnership with Breker to Drive Rigorous Processor-to-System Level Verification for RISC-V | Imperas Software

By July 7, 2022July 11th, 2022No Comments

Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced a partnership with Breker Verification Systems, a leading provider of advanced test content synthesis solutions for SoC, UVM and Post-Silicon verification environments.

With a combined approach to standards-based verification, development teams will be able to efficiently transition from RISC-V processor functional design verification (DV) right through to system level and SoC integration testing, including automated cache coherency validation.

With the new flexibility offered by the open, standard ISA (Instruction Set Architecture) of RISC-V, SoC developers can now optimize a custom processor for domain specific applications. However, the use of these new RISC-V cores introduces additional system level integration verification challenges.

Read the full announcement. 

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.