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TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms | Semiconductor Engineering

By RISC-V Community NewsJuly 4, 2022July 18th, 2022No Comments

New technical paper titled “AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors” from researchers at Technische Universitaet Dresden (TU Dresden).

Read the full article.

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TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms | Semiconductor Engineering

Previous PostFirst RISC-V laptop arrives | Nick Farrell, Fudzilla

Next PostTake note, Arm: The world's first RISC-V laptop is now available for preorder | Joel Khalili, Tech Radar

Stay Connected With RISC-V