RISC-V is a topic that garners lots of interest, but RISC-V itself is nothing more than a scalable, open-source instruction set definition. It’s the implementation that makes things interesting. Though custom ASICs have been the realm for RISC-V implementations, now more application-specific standard parts (ASSP) are showing up. FPGAs that incorporated RISC-V were the first to emerge, but RISC-V ASSP solutions are becoming more generally available.
One example is Renesas’ R9A02G020 motor-control chip that can handle three-phase motors (see figure). The core is an Andes Technology N22 RV32I. This 32-bit integer microcontroller uses the AndeStar RISC-V-compliant V5/V5e instruction set. Leveraging a two-stage pipeline with a mixed 16/32-bit instruction format, it supports branch prediction and hardware multiply/divide. Its StackSafe hardware can be used to measure stack size to detect runtime stack overflow and underflow problems.