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ST to make European octacore RISC-V space chip with selectable cores | Nick Flaherty, EE News Europe

By September 23, 2022No Comments

Space system designer CAES has built the first eight core fault tolerant chip that is selectable between different architectures, including RISC-V.

The radiation hardened GR765 System-on-Chip (SoC) is the first user selectable CPU for space, allowing users to chose the legacy LEON5 SPARC V8 or the new NOEL-V RISC-V RV64 processor cores.

A test chip has been built in Europe on the 28nm FDSOI process technology from STMicroelectronics with both types of cores.

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