Skip to main content
In the News

Andes claims first RISC-V CPU IP with full ISO 26262 compliance, plans DSP version | Nick Flaherty, EE News Europe

By October 17, 2022October 24th, 2022No Comments

Andes Technology has launched a safety-enhanced 32bit RISC-V CPU IP that it says is the first to be certified as fully compliant with ISO 26262 functional safety standards for the development of automotive applications

It is also planning a version with DSP extensions for higher performance early next year.

The AndesCore N25F-SE was assessed by SGS-TÜV Saar for ASIL B (Automotive Safety Integrity Level B) applications, according to all applicable ISO 26262 series of standards including Parts 2, 4, 5, 8 and 9. Andes says all the configurable options are also fully certified so that chip design teams are not limited by one fixed CPU configuration.

The 32bit RISC-V CPU core supports the standard IMACFD extensions, including efficient integer instructions and single/double precision floating point instructions. It incorporates the Andes V5 extension instructions to further boost performance and reduce code size.

Read the full article.

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.