Skip to main content
In the News

French secure element processor uses RISC-V | Nick Flaherty, EE News Europe

By October 12, 2022November 6th, 2022No Comments

French processor designer Tiempo Secure has developed secure IP based on the RISC-V open instruction set.

The TESIC Secure Element IP uses the RV32IMCB 32bit RISC-V specification to adopt a standard architecture alongside its existing proprietary CPU architecture. This will make integration easier for developers who can now use standard development tools, making the integration of its TESIC security elements into system on chip designs faster and easier.

Read the full article.

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.