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Google experiments with RISC-V | Nick Farrell, Fudzilla

By October 1, 2022November 6th, 2022No Comments

SiFive RISC-V chips are being used by Google to run some of its AI workloads and tested in Google datacentres.

SiFive’s Intelligence X280 is a multi-core RISC-V design with vector extensions. When combined with the matrix multiplication units (MXU) lifted from Google’s Tensor Processing Units (TPUs) it is supposed to deliver greater flexibility for programming machine-learning workloads.

So, the RV64 cores in the processor run code that manages the device, and feeds machine-learning calculations into Google’s MXUs to finish it all off. The X280 also includes its own vector math unit.

SiFive co-founder and chief architect Krste Asanović and Google TPU Architect Cliff Young, wrote in his bog that following the introduction of the X280, some customers started using it as a companion core alongside an accelerator, in order to handle all the housekeeping and general-purpose processing tasks that the accelerator was not designed to perform.

Read the full article.

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