Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core | Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi and Mauro Olivieri
Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event upset (SEU) faults. In microprocessors, functional redundancy may be achieved through multi-core or simultaneous-multi-threading architectures, with techniques that are broadly classifiable as Double Modular Redundancy (DMR) and Triple Modular Redundancy (TMR), involving the duplication or triplication of architecture units, respectively. RISC-V plays an interesting role in this context for its inherent extendability and the availability of open-source microarchitecture designs. In this work, we present a novel way to exploit the advantages of both DMR and TMR techniques in an Interleaved-Multi-Threading (IMT) microprocessor architecture, leveraging its replicated threads for redundancy, and obtaining a system that can dynamically switch from DMR to TMR in the case of faults. We demonstrated the approach for a specific family of RISC-V cores, modifying the microarchitecture and proving its effectiveness with an extensive RTL fault-injection simulation campaign.
Previous PostRISC-V Hibernation Support / Suspend-To-Disk Nears The Linux Kernel | Michael Larabel, Phoronix
Next PostTCADer: A Tightly Coupled Accelerator Design framework for heterogeneous system with hardware/software co-design based on RISC-V | Wenqing Li, Tianyi Liu, Ziyuan Xiao HanQi, Weipu Zhu, Jian Wang