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Exploring the Benefits of RISC-V ISA for Posit Arithmetic at HiPEAC Conference | Federico – The AI Blog

By January 5, 2023January 10th, 2023No Comments

I am excited to announce that I will be giving a talk at the HiPEAC conference on the RISC-V ISA for posit arithmetic! HiPEAC is a leading conference in the field of computer science, focused on the design and implementation of high-performance and embedded systems.

As a researcher in the field of computer science, I am thrilled to have the opportunity to present my work on the RISC-V ISA at such a prestigious conference. Posit arithmetic is an alternative to traditional floating-point arithmetic that has gained popularity in recent years due to its improved accuracy and efficiency. The RISC-V ISA has the potential to significantly enhance the performance of posit arithmetic, and I am excited to share my findings with the HiPEAC community.

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