How often have we had to learn a new processor architecture and development environment because our new project requires more horsepower and speed than previous projects? Experience teaches us that similar parts as those with which we are familiar in a new processor can at least ease the pain. But what if learning just one new architecture can position you for quicker and easier designs in the future? Thanks to the RISC-V scalable, replicable, and configurable open-source processors, this is no longer a pipe dream.
Reduced Instruction Set Computers (RISC) are not new architectures; they have been around for decades as a streamlined alternative to the Complex Instruction Set Computers (CISC) that preceded them. Older CISC processors worked very well and, for the most part, followed a Von Neumann architecture where a processor’s code would operate in cycles to fetch, decode, and execute the instructions. RISC processors follow a Harvard architecture where the instruction code bus is separated from the data bus, allowing simultaneous access that lets the processor perform each instruction in a single cycle. This makes them fast, deterministic, and easier for you to create compilers and libraries of functions that could more easily port from machine to machine.