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Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community |

Industry-leading Synopsys VCS simulation and Verdi hardware/software debug solutions accelerate verification and validation of RISC-V cores.

Bluespec Inc., announced today a collaboration with Synopsys to provide Synopsys reference methodologies for verification and hardware/software debug of RISC-V system designs with Bluespec RISC-V cores. As the open and extensible RISC-V Instruction Set Architecture (ISA) continues to see growing adoption, the demands for functional verification of RISC-V-based SoCs is also increasing. This collaboration provides the RISC-V community with proven flows that can be used to accelerate the verification and software/hardware debug of RISC-V processors and systems.

The first phase of the collaboration supplies reference methodology and scripts for Synopsys VCS® functional verification solution and the Synopsys Verdi® Debug System with Bluespec. These reference methodologies are Universal Verification Methodology (UVM) compliant, allowing mutual customers to seamlessly integrate into their verification flows. In addition, Synopsys and Bluespec are working on additional reference methodologies for static, formal, portable stimulus and FPGA synthesis.

“Creating custom implementations of a RISC-V-based ISA requires significant focus on achieving the highest verification coverage possible,” Kiran Vittal, senior director of Partner Alliances in the EDA Group at Synopsys. “Collaborating with key ecosystem companies, such as Bluespec, offers customers the ability to jumpstart their RISC-V designs with Synopsys’ optimized EDA flows and methodologies that will help increase verification productivity, performance and throughput.”

“RISC-V is providing an unprecedented number of CPU options, from suppliers to microarchitectures to custom instructions and more,” said Charlie Hauck, CEO of Bluespec Inc. “We are happy to be collaborating with the EDA leader Synopsys to provide straightforward design, verification and validation flows to safely and efficiently navigate the RISC-V landscape.”

Read the full announcement.

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