Oxford, United Kingdom, October 30, 2023 — Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Tenstorrent, a next-generation computing company that builds computers for AI, has collaborated with Imperas to make available a model of the Tenstorrent Ascalon processor core as part of the Imperas RISC-V model library. As with other areas of abstraction during the complex SoC design process, software simulation provides a functional representation as a programmer’s view of the hardware – this allows an early-stage evaluation of some design options, firmware, and driver development and offers unique access for debugging and analysis. The models of Tenstorrent IP, available as part of Imperas simulation solutions, supports many time-critical aspects of SoC development and helps address the time-to-market and time-to-volume factors for SoC developers adopting Tenstorrent IP.
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