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Video: Leveraging the RISC-V efficient trace (E-Trace) standard

By January 16, 2024February 15th, 2024No Comments

Understanding program behavior in complex systems is not easy. Understanding the behavior of complete systems is even more challenging. Get non-intrusive, full-speed and system-level visibility with E-Trace.

Processor trace gives developers access to critical insights and forensic capabilities to manage the risk of building embedded systems. Efficient Trace for RISC-V (E-Trace) was the topic of a well-attended presentation at the RISC-V Summit held on November 7-8 in Santa Clara, CA. Iain Roberston, Senior Director of hardware engineering in the Tessent group at Siemens EDA delivered “Leveraging the RISC-V efficient trace (E-Trace) standard.” His 17-minute presentation was recorded and is now available on-demand.

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