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A Striped Bus Architecture for Minimizing Multi-Core Interference

By April 17, 2024April 18th, 2024No Comments

Understanding the intricacies of software timing behaviour is crucial, especially in safety-critical systems and systems with real-time requirements. While analysing timing on single-core processor architecture might seem straightforward, the landscape becomes notably more complex when dealing with multiple cores. Here, contention for shared resources such as caches, buses, and peripherals add layers of uncertainty to the timing analysis. In this blog post we describe the on-chip bus architecture of the GR765 octa-core LEON/RISC-V microprocessor. This infrastructure is designed to improve the system performance, minimize multi-core interference, and simplify the worst-case execution time analysis.

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