This project aims to design and integrate the integer “Multiplication and Division Unit (MDU)” with…
RISC-V Community NewsAugust 23, 2021
Content from the RISC-V Community, Ambassadors, Members, and Team
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This video explains the RV32I R-Type instructions. RISC-V is growing rapidly, follow this RISC-V video…
Maven SiliconAugust 17, 2021
The RISC-V Zfinx Task Group is thrilled to announce the Zfinx extension (pronounced “z-f-in-x”) has…
Stephano CetolaAugust 10, 2021
At Starfive Technology, we have been committed to promoting the development of the global RISC-V…
Selina ZhengAugust 5, 2021
The seL4 Foundation and RISC-V International are pleased to announce that Ryan Barry from UNSW…
Gernot HeiserAugust 3, 2021
(点击这里查看原文)由上海科技大学和中国科学院软件研究所联合主办，中国RISC-V产业联盟（CRVIC）、中国开放指令生态联盟（CRVA）、CNRV社区协办的第一届「RISC-V中国峰会」于日前盛大开 ...
Wanxiang BlockchainAugust 3, 2021
This summer, I got the opportunity to work as a Formal Verification Intern with Axiomise…
Shivani ShahJuly 20, 2021
Verilator is a high performance, open source functional simulator that has gained tremendous popularity in…
Rob MainsJuly 19, 2021
There are now over a hundred RISC-V CPU cores listed in the RISC-V Exchange! Amazing.…
Steve HooverJuly 14, 2021
This video shows how we can implement the Multiplication using add and shift RV32I instructions.…
Maven SiliconJuly 12, 2021