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RISC-V Security Forum 2021 – Schedule Announced!

By March 17, 2021April 28th, 2021No Comments

The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events – providing technical content to the RISC-V community.

Our first Forum is on Security, April 14, 7-10am Pacific Daylight Time. Registration is open and complimentary to both members and non-members.

With the many exciting things happening in the Security area, we have an amazing agenda that covers the latest trends on Security, how people are using the tools in the RISC-V ecosystem, and how you can get involved and use the tools.

Thank you to our sponsor Technology Innovation Institute.

Take a look at the agenda below and refer to the event agenda for full details: 

  • Helena Handschuh from Rambus Inc. will kick off the event with a security overview as well as Updates from the Security Response Team, Scalar Cryptography extension, Crypto K, Blockchain & IoT, and FIPS and CC.
  • OpenSBI Domain Support: This talk from Anup Patel of Western Digital will focus on the OpenSBI domain support which was added to the OpenSBI project in the v0.9 release. It will also include a demo showing a small trusted bare-metal application running in its own domain along with Linux running as a separate domain.
  • On the Efficiency of RISC-V Cryptographic Instruction Set Extensions: Tolga Yalcin & Gorkem Nisanci from Northern Arizona University will cover their research where they implemented various algorithms with and without the proposed extensions, including a generic RISC-V core, and present the results.
  • Trusted RV: Trusted Execution Environment, Secure Coprocessor, and their Programming: In this talk, Kuniyasu Suzaki from AIST explains the total secure implementation of TEE consisting of the programming and management environment of Trusted RV.
  • Using PMP, ePMP and Rust to protect embedded kernels, even from themselves: This talk from Alistair Francis at Western Digital will discuss the work done with Tock (an embedded Operating System) to utilize the RISC-V PMP and ePMP to both enforce W^X on kernel memory and to also isolate untrusted applications from the kernel. It will go into details of what protections this provides us and importantly what it doesn’t protect against.
  • Information Flow Confidentiality and Integrity on a Rocket RISC-V SoC: Greg Sullivan from Dover Microsystems will demonstrate use cases around protecting the integrity of an eFPGA bitstream and the confidentiality of AES keys
  • Timesecbench: a work in progress benchmark suite to assess timing leakages: In this talk, Ronan Lashermes from INRIA will discuss the goals, the challenges, and give a glimpse of how the benchmarks work.
  • What in RISC-V IOPMP: Shan-Chyun Ku from Andes Technology will cover the work from the TEE Task Group including the several major functions and features that an IOPMP should be capable of.
  • A Trusted OS for RISC-V? OP-TEE is a candidate: Several products varying from mobile, automotive, and industrial, rely on TEE to protect sensitive information integrity and confidentiality. OP-TEE is an open-source project which offers a secure OS able to run on TEE as a companion to a non-secure OS (Linux, Android). Marouene Boubakri from NXP will cover the patches to be made available to the community.
  • RISC-V Based Secure Flight Computer System: Dr. Shreekant Thakkar from the Secure Systems Research Centre will discuss the project to develop an open RISC-V-based SoC architecture and software stack for adoption on secure application processors for drone flight computer applications.

Live Q&A! Many sessions will have time for attendees to ask questions.

Join us for the RISC-V Security Forum on April 14!

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