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A few months back, I came across a workshop titled ‘RISC-V based Microprocessor for You in Thirty Hours (MYTH)’, that was about designing RISC-V core using TL-Verilog organized by Steve Hoover and Kunal Ghoshin just 5 days!! TL-Verilog must be magic to make this possible? Now I know the magic, and after completing the workshop, I was even more curious to know how we can use TL-Verilog for FPGA and thought of implementing my RISC-V core on FPGA.

Through this workshop, I came to know about how TL-Verilog is a Verilog implementation of TL-X, a language extension defined as a wrapper to any HDL to extend it with transaction-level modeling.

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