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RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V International

By July 11, 2022July 12th, 2022No Comments

In Spring 2022, various mentorship projects were offered by RISC-V International on the LFX platform of the Linux Foundation. I got selected for one of the projects, which is titled Compressed Instructions for SERV. This project aims to add support for RISC-V Compressed Extension onto the base ISA of the SERV CPU. In this mentorship program, I get to work with my mentor Olof Kindgren, who is the father of SERV and also the director and co-founder of the FOSSI Foundation. This mentorship program went from March 2022 to May 2022.


RISC-V is the open-source, royalty-free Instruction Set Architecture (ISA) which was developed in 2010 as a summer project at the University of California, Berkeley. The ISA has the specification for 32-bit and 64-bit instructions. It has a modular design that comprises of base ISA along with the optional extension. The base ISA comprises Integer (I) instructions. Some common standard extensions include C for ‘Compressed instructions’, M for ‘Integer Multiplication and Division’, Zicsr for Control and Status Register (CSR), and Zifence. There are two categories of RISC-V ISA: privilege and user-space which is now called un-privilege ISA.



Why Compressed extension…

Compressed extension for SERV

serv_aligner checks the address of the instruction. If it is aligned, it will just pass the signals from SERV to Memory and vice versa. serv_aligner comes into action whenever the misaligned address is encountered. For the misaligned memory access, serv_aligner first fetches the aligned instruction at address pc-2 and stores the upper half-word [31:16] of this instruction in a register. Then it makes another bus transaction and fetches the aligned instruction at pc+2 and concatenates its lower half-word [15:0] with that of the previously-stored half-word. And the concatenated instruction is passed to the SERV core by enabling the acknowledge signal. Note that, pc is the program counter or address of the current misaligned instruction. The instruction cycles for two cases of serv_aligner are illustrated in the following figure.

Handling misalignment using serv_aligner


The hardware design of the serv_aligner module is given in the following figure.


Hardware design of SERV aligner

Compressed SERV

Compressed SERV in action

pip install fusesoc
fusesoc library add serv
fusesoc run --target=lint serv
INFO: Preparing ::serv:1.1.0
INFO: Setting up projectINFO: Building simulation model
verilator -f -Wall
INFO: Running
fusesoc run --target=verilator_tb servant --compressed=1 --uart_baudrate=57600 --firmware=/path/to/hex --memsize=16384
fusesoc run --tool=icestorm serv --pnr=none
fusesoc run --tool=icestorm serv --pnr=none --COMPRESSED=1

Testing and Verification

fusesoc run --target=nexys_2_500 servant --compressed=1 --memfile=/path/to/hex

The Zephyr terminal shows the hello world message on the serial monitor as follows

fusesoc run --target=verilator_tb --build servant --memsize=8388608 --compressed=1
git clone --branch 2.7.4
cd riscv-arch-test && make TARGETDIR=$SERV/riscv-target RISCV_TARGET=serv RISCV_DEVICE=C TARGET_SIM=$WORKSPACE/build/servant_1.1.0/verilator_tb-verilator/Vservant_sim

At the time of implementing the support of Compressed instructions, the arch tests were updated to version 2.7.4. Some more privilege tests were added in the arch-test suit. So, the SERV core was also updated to support and pass those newly added privilege tests. Privilege tests can be verified by setting RISCV_DEVICE=privilege.


  • Added support of RISC-V Compressed Extention to SERV. See here.
  • Updated SERV to make it pass the privilege compliance tests.
  • Added support of new target FPGA board — Nexys 2 — to fuseSoC blinky to believe project. See here.
  • Added support of Nexys 2 FPGA board to the SERVANT. See here.
  • Future work: Update the documentation of SERV.


Photo by Matt Jones on Unsplash

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