2022 has been an incredible year for RISC-V, the open-standard Instruction Set Architecture (ISA) that is unleashing a new wave of innovation in computing. With 10 billion cores already shipped, the freedom that RISC-V enables is catalyzing a huge range of new products and tools across a wide range of application areas from low-end embedded processing to the data centre, used in locations from the home, to our cars, to outer space.
The RISC-V ecosystem is the next big thing in computing, quickly building in strength and numbers, and the RISC-V Summit, 13-14 December 2022 in San Jose (and virtual too) is where we all come together to learn and to discuss the future. Alongside sessions detailing the road ahead and the technical development of the architecture we have a range of keynotes, talks, demonstrations and tutorials across a diverse set of application spaces and subjects, as well as an expo hall where you can meet companies from across the RISC-V ecosystem. Let’s look at some of the news from 2022, and the Summit sessions and activities that help look ahead to 2023.
RISC-V in Space
2022 marked the first RISC-V processor in space! The Trisat-R nanosat, developed by the University of Maribor, used a processor developed by CAES, implemented in an FPGA. In other amazing space news, NASA partnered with Microchip and SiFive to create the High Performance Spaceflight Computing (HPSC) chip based on RISC-V. Come to RISC-V Summit to find out more, where a member of the HPSC leadership team will deliver a keynote on space-based computing. Other related talks include a session detailing RISC-V in aerospace and defense applications, and a keynote from Microchip discussing edge applications from ground to space.
Closer to home, our cars are undergoing a digital transformation, an opportunity made possible through safety-enabled computing. This year, new automotive RISC-V CPUs and partnerships were announced by Andes, SiFive, Imagination Technologies and NSITEXE, alongside tool and development support from IAR, Green Hills Software and Lauterbach. This momentum continues at RISC-V Summit, with a keynote on how to avoid Murphy’s Law in automotive, a panel of industry experts discussing the RISC-V automotive ecosystem, talks on heterogeneous compute, software safety qualification, and open-source automotive innovation, along with a demo of dual-core lock step RISC-V processors.
Android on RISC-V
A key piece of software support that will enable future RISC-V devices came with the news that the Android Open Source Project (AOSP) had been ported to the RISC-V architecture. Android is the operating system for a range of devices, including smartwatches, smartphones and tablets. Attendees of the RISC-V summit can hear more in a keynote from Google Director of Engineering, Lars Bergstrom, and a technical talk from Mao Han of Alibaba.
In the Data Centre
The data center is where more and more computing happens, requiring heterogeneous solutions with specialized elements for different jobs. Andes launched the high end AndesCore AX65core for applications including data centre accelerators, networking and storage, while Ventana Micro announced it had raised $55 million in funding to productize its RISC-V based chiplets targeting datacentre infrastructure applications. SiFive announced that its Intelligence™ X280 processor is being “used as the AI Compute Host to provide flexible programming combined with the Google MXU (systolic matrix multiplier) accelerator in the datacenter”. In other high performance computing news, a European team of university students started experimenting with the first RISC-V supercomputer capable of showing balanced power consumption and performance. At RISC-V summit there is a session discussing “RISC-V Readiness for Datacentre”. Another explores high-performance processors for server applications, while a demo in the exhibit hall showcases storage acceleration.
AI and ML continued to be big news this year. Untether AI in Canada developed Boqueria, a device with over 1400 RISC-V processors to optimize energy and compute density, while Esperanto announced its AI accelerator, ET-SoC-1, with over 1000 RISC-V cores. This SoC will be discussed at the RISC-V Summit, as well as a range of other AI and ML topics including “The Future of AI with RISC-V” and “HW-SW co-development for RISC-V based ML secure systems”. These talks, alongside additional demos and technical sessions will give visitors an extensive understanding of the potential of RISC-V for AI and ML applications.
Chips and Boards
This year saw many exciting new chips and boards, at a range of price points and capabilities, to fire the imaginations of the developers worldwide. WCH launched a sub-10 cent RISC-V microcontroller alongside a low cost development board, while Espressif announced the ESP8684 MCU, enabling WiFi and BLE in a 4mm x 4mm package. Intel Pathfinder for RISC-V enabled software developers and SoC architects to access a range of RISC-V cores, surrounding IP, operating systems, and toolchains, enabling them to test and evaluate their designs before they are committed to silicon. At RISC-V Summit, there are a range of talks and tutorials for both hardware and software developers, covering a range of subjects including tools, verification, testing, performance analysis, power management and security.
2022 has been an amazing year for the RISC-V ecosystem, and its momentum continues to accelerate. RISC-V enables the best processors for any application, and the community is quickly building the strongest ecosystem to support developers around the world. As impressive as this year has been, next year will be bigger and better. Give yourself a head start by attending RISC-V Summit, on 13th & 14th December 2022.