Skip to main content

Exploring the Top Highlights of the RISC-V Booth at embedded world 2024

embedded world 2024 showed great momentum for RISC-V. Throughout the event, RISC-V International members showcased cutting-edge innovations and forged invaluable connections, expanding the reach of RISC-V across diverse markets and applications.

At the heart of the action was the RISC-V stand in Hall 5, featuring eight dynamic demo kiosks where visitors engaged with our sponsoring members firsthand. Additionally, the Demo Theatre served as a hub for illuminating talks, unveiling the latest advancements in a captivating series of presentations. Presentations will be available on the RISC-V YouTube channel in the coming days. Until then, you can access the program of talks and slides here.

Let’s dive into the highlights from embedded world 2024:


  • Andes discussed how RISC-V is revolutionizing AI, highlighting applications beyond Large Language Models, where it could be used from endpoints to the datacenter. This includes 5G networking and SSD controllers, which can be addressed with AndesAIRE solutions. Andes also highlighted some AI design successes, including Renesas R9A06G150 Voice-Control ASSP, Spacetouch SPV60 Intelligent audio processor, and the MTIA: Meta Training and Inference Accelerator. In addition to AI, Andes’ second session focused on RISC-V in HPC, discussing how their innovative CPU IP boosts performance by reaching higher frequencies and consuming less power. Furthermore, their high-performance RISC-V vector application processor can address edge AI and HPC applications.


  • showcased their RISC-V developer boards, both of which were featured in our Developer Zone where visitors could interact with the latest RISC-V-based boards. The BeagleV-Ahead targets high-performance mobile and edge intelligence applications, boasting an Alibaba T-Head TH1520 SoC and a retail price of $149. The BeagleV-Fire is tailored for ultra-low latency industrial control applications, equipped with a Microchip Polarfire SoC, and also priced at $149.


  • MachineWare teamed up with Codasip to discuss Fast Virtual Platforms for Custom RISC-V Processors. As semiconductor scaling approaches its limits, the demand for custom compute arises to facilitate domain-specific architectures. RISC-V emerges as the prime choice for such processing due to its open and customizable nature. Codasip Studio, in collaboration with MachineWare SIM-V, offers an integrated solution for seamless entry into custom compute, fostering hardware/software co-design and pre-silicon software development. In their subsequent session, MachineWare delved into their Virtual Platform technology, elaborating on how their VPTrace tool facilitates code coverage analysis in diverse applications, such as automotive.


  • The OpenHW Group is a non-profit organization with a mission to host and curate high-quality RISC-V cores and IP for industrial usage. During their presentation, they detailed their CVE2, CVE4, and CVA6 core families, discussing their supporting deliverables and roadmap. They also introduced their MCU development kit, which is currently available in limited quantities for evaluation purposes.


  • Renesas introduced their brand new RISC-V general-purpose MCU, the R9A02G021, an energy-efficient and performant Renesas RISC-V 32-bit core, suited for cost-sensitive and low-power applications. This new MCU is based on Renesas’ own CPU design, and after their talk they gave away 100 FPB-R9A02G021 Fast Prototyping boards based on this new MCU. The board is available from Renesas now.


  • Semidynamics, a European supplier of RISC-V IP cores, specializes in customizing high-bandwidth, high-performance AI cores for specific projects. During their presentation, they elaborated on their approach of integrating CPU, gpGPU, and NPU to create a high-performance AI solution. This integration aims to simplify programming, eliminate latency, improve PPA, and enable unified programming through a single software stack.


  • Siemens discussed how to leverage the RISC-V Efficient Trace (E-Trace) standard. Understanding program behavior in complex systems can be challenging, requiring non-intrusive, full-speed, efficient observation of program behavior. E-Trace for RISC-V addresses this problem while Siemens Tessent Embedded Analytics enables system-wide real-time debug and post-deployment analytics for complex system-on-chips, providing intimate visibility of the real-world behavior of entire systems, while the Tessent Embedded SDK  is a software library that enables the creation of a self-contained monitoring and analytics environment on-chip.


  • SiFive introduced their new HiFive Premier P550 development system, a high-performance RISC-V development board based on a quad-core SiFive Performance P550 core complex. It features a quad-core application processor featuring a thirteen-stage, triple-issue, out-of-order pipeline with the RISC-V RV64GBC ISA, on-board LPDDR5, eMMC, and PCIe Gen3. This premium software development system comes in a modular design with the use of a System-On-Module (SOM) and 13.3 TOPS AI computing power and is designed for applications like machine vision, intelligence video analysis, AI PC, and servers.


  • Synopsys discussed their ImperasFPM Fast Processor Models which enables verification, architecture exploration, and software development. These models are used across the design process, from architectural exploration of custom instructions to system modeling of complex multicore designs. They enable early execution of the target software stack meaning easier development of customised hardware and reduced time to market as well as successful verification and design closure. Synopsys also outlined their ARC-V™ Processor Family, high-quality, configurable, and extensible processors with excellent PPA to meet diverse application requirements and handle the latest workloads.


  • Tiempo Secure explored the role of the Secure Enclave in IoT and digital applications. Guaranteeing robust embedded security measures has become paramount in the rapidly evolving landscape of IoT, AI, Data Centers, Automotive, and Digital Applications. The Secure Enclave is the cornerstone of embedded security for the next generation of SoC, ASIC, and application processors. Their TESIC-300 and TESIC-500 Secure Enclaves ensure and offer secure sub-systems to protect against various forms of physical and logical attacks, ensuring the integrity and security of the overall system. Tiempo’s second talk outlined the use of TESIC in automotive applications where high safety and security levels are critical.


  • Technology Innovation Institute also discussed security in their talk about what they see as the next evolution of security – zero trust. While designers maximize their efforts to construct highly secure systems, clever attackers tend to find ways to intercept the functional design. Because of this, they need to anticipate that some parts of a chip could be compromised, meaning zero trust between the components. The trust needs to be earned every time. Their Al Saqr chip for drone applications, taped-out Feb 2024, implements zero trust to address today’s sophisticated threat landscape and paves the way for Zero Trust’s wider adoption in chip design.


embedded world 2024 proved to be an incredible event, drawing increased interest from attendees eager to learn more about RISC-V. The showcased power of open collaboration promises to unlock unprecedented levels of innovation across various application domains. We are looking forward to next year’s events!

We would like to thank our Premium Sponsors for their support of RISC-V at embedded world 2024!



Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.