About this event RVfpga (RISC-V fpga) Understanding Computer Architecture – A Hands-On, In-Person, One-Day-Workshop Bring RISC-V to your course in computer architecture using RVfpga This workshop shows how...
This webinar will be presented in Japanese. This webinar will introduce the overview and configuration of the RISC-V verification environment, while presenting actual examples from NSITEX, an industry leader in...
RISC-V Reshape the World, Focusing on Strategic Layout of AI, Automotive, Android Date: 2023/5/16 (Tue) Time: 13:30 - 17:10 (GMT+8) Location: Ambassador Hotel Hsinchu, 10th Floor
Co-located with ISC 2023, this is a half day workshop aims to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool...
The RT-Thread Global Tech Conference (RGTC) is an annual event that brings together developers from around the world to focus on the latest developments in RT-Thread basic software technology and...
The RT-Thread Global Tech Conference (RGTC) is an annual event that brings together developers from around the world to focus on the latest developments in RT-Thread basic software technology and...
Event Profile This event aims to provide comprehensive RISC-V open source technology training and RISC-V international certification exam for technology enthusiasts in first-tier cities in China. During the event, RISC-V...
The last thing you want to do when adding custom instructions to your RISC-V design is to unintentionally insert some deep corner case bug – the kind of bug that’s...
Time：Oct 28th - Oct 29th 2023, 9AM - 5PM on each day地点：Conference Room 211, Shaw Science Museum, Yuquan Campus, Zhejiang University (浙江大学玉泉校区邵逸夫科学馆 211 会议室)*The workshop will be in Chinese；将会用中文授课 Register...
Time：Oct 28th - Oct 29th 2023, 9AM - 5PM on each day地点：Conference Room 211, Shaw Science Museum, Yuquan Campus, Zhejiang University (浙江大学玉泉校区邵逸夫科学馆 211 会议室)*The workshop will be in Chinese；将会用中文授课 Register...
In recent years, the field of processor chips is undergoing a revolutionary change. The core of this change is RISC-V (Reduced Instruction Set Computer-V), a new instruction set architecture. RISC-V...
Right after RISC-V Summit North America, join us in nearby Sunnyvale for the next CHIPS Alliance Technology Update featuring informative, technical talks on open source hardware / ASIC collaborative development,...
We send occasional news about RISC-V technical progress, news, and events.
