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LowRISC Blog Post: Barcelona RISC-V Workshop: Day Two

By May 9, 2018May 12th, 2021No Comments
The eighth RISC-V workshop is continuing today in Barcelona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day.Look back here for the day one live blog.

Fast interrupts for RISC-V: Krste Asanovic

  • Embedded is a major use for RISC-V. There is a desire for faster interrupt handling with support for nested preempted interrupts.
  • Summary of current RISC-V interrupts
    • Local interrupts are directly connected to one hart. There’s no arbitration between harts to service. Determine cause through xcause CSR. Only two standard local interrupts (software, timer).
    • Global (external) interrupts are routed via the platform-level interrupt controller (PLIC) which arbitrates between multiple harts claiming an interrupt.
  • The machine interrupt pending (mip) CSR contains bits for local software, local timer, and external interrupts (from the PLIC). It tells you which interrupts are present.

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