Fast interrupts for RISC-V: Krste Asanovic
- Embedded is a major use for RISC-V. There is a desire for faster interrupt handling with support for nested preempted interrupts.
- Summary of current RISC-V interrupts
- Local interrupts are directly connected to one hart. There’s no arbitration between harts to service. Determine cause through xcause CSR. Only two standard local interrupts (software, timer).
- Global (external) interrupts are routed via the platform-level interrupt controller (PLIC) which arbitrates between multiple harts claiming an interrupt.
- The machine interrupt pending (mip) CSR contains bits for local software, local timer, and external interrupts (from the PLIC). It tells you which interrupts are present.
To read more, please visit: http://www.lowrisc.org/blog/2018/05/barcelona-risc-v-workshop-day-two/