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See Esperanto Technologies At The Inaugural RISC-V Summit, December 2018

By November 16, 2018May 12th, 2021No Comments

Esperanto Technologies, developer of high-performance, energy-efficient computing solutions based on RISC-V for artificial intelligence (AI), machine learning (ML) and Deep Learning (DL) applications, today announced its sponsorship of the RISC-V Summit. Esperanto will also speak at this event, and invites you to “Join the RISC-V Revolution!” to be part of the disruptive force transforming the microprocessor IP market through open standard collaboration.

  • What: RISC-V Summit.
  • Where: Santa Clara Convention Center, 5001 Great America Pkwy, Santa Clara, California.
  • When: Conference and Exhibition Dec. 4-5. Pre-Conference Day Dec. 3. RISC-V Foundation Members Meeting Dec. 6.
  • Agenda: View the agenda here.

The RISC-V Summit 2018 will feature an Esperanto exhibit, as well as a technology presentation on a RISC-V based processor design.
Presentation: The Esperanto ET-Maxion™ High Performance Out-of-Order RISC-V Processor

  • Authors: Polychronis Xekalakis and Chris Celio, CPU Architects at Esperanto Technologies.
  • This talk presents an update on ET-Maxion, a high-performance out-of-order RISC-V core which is being designed for TSMC’s 7nm process. It describes the key micro-architectural features that allow ET-Maxion to achieve performance levels comparable to existing commercial high-end processors, and discusses design choices, including shielding against timing attacks such as Spectre and Meltdown, with negligible performance sacrifices. Experiences in implementing the RISC-V compressed instructions (RVC) and the weak consistency model (RV-WMO) in a superscalar out-of-order core, along with design challenges, are shared. Finally, a brief overview of support for post-silicon debug and planned performance monitoring improvements for ET-Maxion.
  • Read more: See the complete presentation abstract here.

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