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EEJournal Article: Priming The RISC-V Pump

By January 28, 2019May 12th, 2021No Comments

We’re probably all aware at some level of the new processor upstart, the open-source RISC-V instruction set architecture, which means, if you want to use it, and you’re starting from scratch, then there are lots of steps necessary to do anything.
It’s easy to think that you can simply go out and buy these handy new RISC-V chips, which will cost less due to the open source platform. But, while excitement is high, an ISA must be turned into an architecture and a micro-architecture, to be followed by detailed chip design and fabrication just for the core. Then you need the whole subsystem, which gives you a shot at developing a chip. Try to use that chip, and you have to host an operating system and then create code, apply middleware, install communications stacks and debug everything.
Of course, if you’ve heard of RISC-V, then you’ve probably heard of SiFive, the first really visible company to commercialize RISC-V. But does that mean that this will become yet another single-sourced processor? What if there were options when there is a deep community with real competition?
There are a couple of things buried in that last question: community and competition. NXP has an opinion on the state of the community, and they’re doing some work (for free, at least at present) to build more community. As far as I can tell, their goal isn’t specifically to create more competition, but that could be a side effect of a robust community.
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