The hardware description of the SSD controller SweRV from Western Digital is now available as open source. The controllers first introduced the company at the end of last year. In the future, these will no longer be based on the ARM command set from the manufacturer of the same name but rely on the free CPU command set RISC-V. Well in the sense of the open source cooperation of the RISC-V members are now also the actual chips of Western Digital Open Source or Open Hardware.
The designs now available are a 32-bit RV32I-compliant design. Western Digital’s documentation also supports a multiplier unit and compressed commands. Added to this are a few other standardized registers (CSRs), the ability to coherently load commands, and a branch prediction unit.
To read more, please visit: https://www.golem.de/news/swerv-western-digital-legt-eigene-risc-v-designs-offen-1901-139004.html. Please note that the original article is in German.