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Andes Technology Announces RISC-V Single-Core And Multicore Processors With DSP Instruction Set

By March 12, 2019May 12th, 2021No Comments

At the RISC-V Workshop Taiwan cohosted by Andes Technology today, Andes proudly announces the debut of its 32-bit A25MP and 64-bit AX25MP RISC-V multicore processors. The A25MP and AX25MP are the first commercial RISC-V cores with comprehensive DSP instruction extension. With the addition of cache-coherent multiprocessors and the DSP ISA based on the RISC-V P-extension draft Andes donated to the RISC-V Foundation, Andes brings powerful solutions to address the new market and further enriches its RISC-V lineup.
Multiple processor cores working in parallel empower applications such as artificial intelligence and Advanced Driver-Assistance Systems (ADAS) to boost performance of their computation intensive tasks significantly. Furthermore, hardware managed cache coherence simplifies software design considerably for systems with multiple CPUs. The A25MP and AX25MP support up to four CPU cores. They provide efficient cache coherence among private level-1 caches; include an optional shared level-2 cache; and support I/O coherence for bus masters without caches. Operating at over 1GHz in 28nm process with Linux symmetric multiprocessing (SMP) support, the A25MP and AX25MP raise the RISC-V processors to the next performance level and a wider market.
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