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L'Embarque Article: Andes Adds RISC-V Processor Core To DSP Instruction Set

By March 20, 2019May 12th, 2021No Comments

Founding member of the RISC-V Foundation, Taiwanese Andes Technology has expanded its RISC-V core catalog with 32-bit, 64-bit multicore models with industry-leading set of instructions for the first time in the industry DSP. A25MP and AX25MP, respectively, these two IP targets computation-intensive applications such as Artificial Intelligence and Driver Assistance (ADAS) where audio and / or video signals and images must also be processed.
In this respect, it is Andes who leads the RISC-V Foundation’s P-Extension working group, which is responsible for bringing a standard DSP instruction set to the RISC-V open source architecture. In this context, the Taiwanese offered his DSP / SIMD instruction set as a starting point and aligned the A25MP and AX25MP on the draft standard. of the working group.
To read more, please visit: Please note that the original article is in French.

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