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UltraSoC Blog Post: The RISC-V Ecosystem Has Many Layers

By May 15, 2019May 12th, 2021No Comments

At our second Bristol RISC-V Meetup last Tuesday, a packed room of 70 delegates joined UltraSoC and Imperas Software, to discuss the latest updates on the RISC-V architecture and ecosystem.
The engaging presentations at the Meetup covered a wide range of topics, including security, compliance, and code size optimization. UltraSoC CTO Gadge Panesar provided a ‘state-of-the-nation’ update from the RISC-V Foundation, as well as addressing some of the issues of systemic complexity posed by today’s large, heterogeneous SoC designs.
This was followed by a wide-ranging presentation from Imperas CEO Simon Davidmann who provided an update on compliance, progress on vector and bit manipulation instructions within RISC-V, and outlined a flow for designing new instructions.
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