EETimes Article: Andes Technology Launches FreeStart To Boost RISC-V Adoption

What’s clear from listening to the community here at the RISC-V Workshop at ETH in Zurich is that the architecture is still in its infancy and a handful of companies is trying very hard to boost adoption, and convince developers of the benefits of the technology.
It’s no surprise then to see the launch of a program encouraging designers to try RISC-V for free, in other words no license fee.  Andes Technology Corporation announced its RISC-V FreeStart program, which chief technical officer Charlie Su said aims to help ‘take RISC-V mainstream’.  The program offers an easy way to build a system-on-chip (SoC) foundation on its commercial-grade RISC-V CPU core N22, available for free download. The AndesCore N22 is an entry-level, low-power RISC-V CPU which delivers a performance of 3.95 Coremark/MHz, which Andes says is the highest in its class. Its configurable features include multiplier, interrupt controller, local memory, instruction cache and debug support. With the RISC-V FreeStart program, SoC engineers can begin designing a RISC-V based SoC without having to budget for CPU IP costs upfront.
 
To read more, please visit: https://www.eetimes.com/document.asp?doc_id=1334808#