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OpenHW Ecosystem Implements Imperas RISC-V reference models for Coverage Driven Verification of Open Source CORE-V processor IP cores

By July 22, 2020April 28th, 2021No Comments

Oxford, United Kingdom, July 21st, 2020 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that OpenHW Group, the not-for-profit global organization set up to facilitate collaboration between hardware and software designers in the development of open-source IP, has established the CORE-V processor verification test bench using the Imperas RISC-V reference model to deliver quality IP cores to the OpenHW Group ecosystem and the open source hardware community. The OpenHW Group CORE-V Design Verification (DV) test plan is available at together with the UVM testbench GitHub repository at
OpenHW RISC-V Imperas Reference Model based DV FlowArticle:

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