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Oxford, UK – December 9th, 2020 – Imperas Software Ltd., the leader in RISC-V processor verification solutions, today announced significant enhancements to its RISC-V processor hardware design verification solutions. This release includes enhanced reference model with SystemVerilog encapsulation / integration and new test bench blocks, new riscvOVPsimPlus™ free simulator, and a range of Imperas developed RISC-V architectural validation tests for the ratified and soon to be ratified RISC-V ISA extensions.

The Free riscvOVPsimPlus RISC-V reference model and simulator, which has been widely adopted across the RISC-V verification ecosystem, has been updated and extended with additional features including full configurable instruction trace, GDB/Eclipse debug support, plus memory configuration options. Additionally, included in the updated model are the full standard CLIC features, Debug Module / Mode, “H” Hypervisor simulation, and also ‘near-ratified’ ISA extensions for Vector “V”, Bit Manipulation “B”, and Crypto (Scalar) “K” extensions.


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