RISC-V International CEO Calista Redmond provided an update on the state of the community during the annual RISC-V Summit: “RISC-V has had an incredible year of growth and momentum. This year, our technical community has grown 66 percent to more than 2,300 individuals in our more than 50 technical and special interest groups. We’re seeing increased market momentum of RISC-V cores, SoCs, developer boards, software and tools across computing from embedded to enterprise.” Early in the coming year, a number of new extensions, including Vector, Bit Manipulation, Scalar Cryptography, Packed SIMD, Secure PMP and Virtual Memory, will undergo public review. Security will be a focus, as well, with a new response process for potential security issues and upcoming cryptography extensions.
Imperas Software added to its RISC-V processor verification solutions with an enhanced reference model with SystemVerilog encapsulation / integration and new test bench blocks, a new riscvOVPsimPlus free simulator, and a range of RISC-V architectural validation tests for the ratified and soon to be ratified RISC-V ISA extensions. To support the SystemVerilog encapsulation of the reference model, the Imperas RISC-V Processor Verification IP (VIP) package includes example SystemVerilog supporting components and modules for interfacing and synchronization between the RISC-V golden reference model and the RTL core under test in a step-and-compare verification flow. The free riscvOVPsimPlus RISC-V reference model and simulator has been updated and extended with additional features including full configurable instruction trace, GDB/Eclipse debug support, plus memory configuration options.