Oxford, UK – March 1st, 2021 – Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced the release of the latest update to the RISC-V architectural validation test suites for the RV32/64K Crypto (scalar) extension. Developed in conjunction with the guidelines of the RISC-V International Architecture Tests SIG, Imperas has achieved an almost 100% functional coverage of the instructions based on the RISC-V Cryptographic Extensions task group’s functional coverage plan. The released tests support the RISC-V ISA Crypto specification proposed as the “K” extension, current draft spec 0.8.1, and will be updated as the spec is publicly reviewed and ratified.
Imperas has uploaded the new test suite to the official RISC-V International GitHub repository, available at https://github.com/riscv/riscv-arch-test, and the riscv-crypto repository is on GitHub at https://github.com/riscv/riscv-crypto.
In addition, Imperas has also updated the free RISC-V Open Virtual Platform Simulator, known as riscvOVPsimPlus™, as a reference Instruction Set Simulator (ISS) for users and developers of RISC V processor cores, with the new Crypto extensions, which is available on OVPworld.