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Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding Premier member of the RISC-V International Association, has certified the Imperas reference models for the complete range of Andes IP cores with the new RISC-V P extension. Developers can now use the Imperas reference models to evaluate multicore design configuration options for SoC architecture exploration.

The open standard RISC-V ISA (Instruction Set Architecture) has a modular structure based on multiple independent extensions that offer dedicated and enhanced functionality to optimize a processor for the target application. The new SIMD/DSP extension, designated as ‘P’ in the specification description, supports efficient data processing applications and real-time requirements. The RISC-V International P Extension Task Group is in the final stages of submitting the specification to the official ratification process, which is expected to be completed within H2 2021.

Read the full announcement here. 

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