CAES, a leader in advanced mission-critical electronics for aerospace and defense, announced today that it has been awarded a contract from Vinnova, a Swedish government agency dedicated to promoting innovation, to develop next generation RISC-V based space computing capabilities. The results from this development will allow future CAES microprocessors to enable spacecraft control, create high performance payload processing and will feature timing isolation for software applications and prevent interference from other parts of the system.

The new NOEL-V fault-tolerant, 64-bit processor core is based on the open RISC-V instruction set architecture and builds upon CAES’ heritage with the SPARC/LEON architecture. It marks the newest addition to CAES’ trusted fault tolerant space computing product portfolio.

Read the full announcement. 

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.