When it comes to designing your own CPU core, you primarily need to get an open-source ISA (instruction set architecture). This open-source ISA will help the CPU understand the programs and execute them accordingly. Most of us have worked with Intel’s x86 ISA, which is not only proprietary but also a CISC (complex instruction set computer), limiting us to use it for our own design. With the increasing popularity of open-source ISAs that can be OpenPOWER or RISC-V, we seeing more people adopting the new RISC-V instruction set architecture because of the support from toolchain vendors to fabricate the chips. Originating from UC Berkeley in 2010, the RISC-V ISA is a lot different from the ARM in terms of the licensing and complexity involved. RISC-V is optimized to the level where the implementation varies from a microcontroller to supercomputers. Even though ARM is well established in the mobile phones and single-board computer (SBC) industries, it won’t take a long time to see RISC-V in the picture. These are some of the significant reasons why RISC-V is considered a threat to ARM architecture. If you are interested in the details of RISC-V ISA, stick around because this is what you want to get started on. Learn all about what RISC-V is and why it could surpass ARM!

What is RISC-V?

In simple words, the RISC-V (pronounced as “risk 5”) is an open-source new instruction set architecture that came into existence for research and educational purposes. However, with the quick adoption and support of the ecosystem, it has become one of the most adopted open ISAs. This open ISA is available to the community that plans to work on hardware implementation and not just simulation or binary translation. The RISC-V instruction set architecture comes with a base ISA, which can be used and customized for educational use. Still, the user can also add optional extensions to make the processor core more powerful.

 

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