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The semiconductor ecosystem is at a turning point for how to best architect the CPU based on the explosion of data, the increased usage of AI, and the need for differentiation and customization in leading-edge applications.

In the past, much of this would have been accomplished by moving to the next process node. But with the benefits from scaling diminishing at each new node, the focus is shifting to architectural and particularly microarchitectural changes to manage tradeoffs like resource allocation, power, throughput, and area. This is putting pressure on EDA vendors to develop a new set of capabilities to optimize power, performance, and area for a complex mix of different tasks and applications. At the same time, it’s rekindling interest in design tools with the kind of “wow factor” not seen in years.

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