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RISC-V Chiplets, Disaggregated Die, and Tiles | Chris Jones, SiFive

By September 22, 2021September 23rd, 2021No Comments

Scalable High-Performance Computing SoC Design with RISC-V

Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules, a growing trend among SoC designers is making the interposer act like a ‘mainboard’ to host multiple chips. Together, these chips form a coherent whole product intended for a specific market and offer both advanced workload performance and efficiency benefits.

The technology industry is shifting to custom designs, replacing traditional general-purpose CPU and discrete accelerator platforms. Instead, the computing platform can implement application-specific processing requirements at many levels, down to the instruction set architecture (ISA). Enabling this industry shift is central to SiFive’s mission and why SiFive’s founders invented RISC-V a decade ago.

Read the full blog post. 

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