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Proposed RISC-V vector instructions crank up computing power on small devices | Agam Shah, The Register

By October 18, 2021October 19th, 2021No Comments

RISC-V looks set to be extended to bring more computing power to applications on smaller devices.

The Zve collection of software instructions, right now under public review, provide vector math processing for embedded devices and microcontrollers.

RISC-V is an open-source, royalty-free instruction set architecture for CPU cores: RISC-V International sets the spec, and semiconductor designers are free to implement it as they see fit in their processors and system-on-chips.

The ISA is structured as a set of extensions, and CPU designers can pick and choose which extensions they wish to implement to suit the software their components will likely run. If you want to make a core capable of natively booting a usable Linux system, for instance, you’ll want to implement at least the base set of integer instructions plus the atomic operations and multiplication and division sets, and a few others for good measure.

The Zve extensions provide 32-bit and 64-bit integer, fixed-point, single-precision, and double-precision floating-point vector operations suitable for modest CPU cores. There is, separately, a full-blown vector math extension that was frozen for public review last month. Zve is a more modest spin of that so that it can be implemented in smaller cores.

“Applications such as AI, vision processing, security and voice will all benefit from the Zve extensions,” said Ted Speers, technical fellow at Microchip Technology, which makes chips with RISC-V-compatible cores.

Read the full article. 

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