Efficient Trace In RISC-V | Ed Sperling, Semiconductor Engineering

By RISC-V Community NewsDecember 19, 2022January 4th, 2023No Comments

Systems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks about what’s needed for debug and trace in context, including the need for unobtrusive observation at full speed, what to trace and when to trace it, and how embedded IP can identify to report which branches are taken and which ones aren’t.

Read the full article.

Previous PostServer-class RISC-V Core Unveiled by Ventana at RISC-V Summit | Aaron Carman, All About Circuits
Next PostHow RISC-V has become a viable third processor architecture | Dean Takahashi, Venture Beat

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.

Efficient Trace In RISC-V | Ed Sperling, Semiconductor Engineering

Previous PostServer-class RISC-V Core Unveiled by Ventana at RISC-V Summit | Aaron Carman, All About Circuits

Next PostHow RISC-V has become a viable third processor architecture | Dean Takahashi, Venture Beat

Stay Connected With RISC-V