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MIPS Rolls Out Its First RISC-V Processor Core – It’s a Big ‘Un | Steve Leibson, EE Journal

Even though the company had telegraphed its big move, MIPS’s adoption of the RISC-V ISA for its future processor cores hit me like a ton of bricks. MIPS is one of the heroes of the early RISC revolution, and the company has gone through a lot of ups and downs. Big ups. Big downs. Jim Turley discussed the MIPS announcement about joining the RISC-V gang last year. (See “Wait, What? MIPS Becomes RISC-V.”) Last month at the RISC-V Summit, MIPS rolled out its first RISC-V core – the eVocore P8700 – an OOO (out of order) execution, multithreaded, 64-bit processor core designed for servers. The P8700 core will scale to 64 clusters with 512 processor cores in total, supporting 1024 harts (RISC-V hardware threads). In addition, MIPS announced its first P8700 customer, autonomous vehicle (AV) computer maker Mobileye.

The Mobileye announcement isn’t all that surprising because Mobileye has been using MIPS CPU cores in its AV SoCs for a decade. With the new P8700 core, Mobileye gets an OOO execution speed boost, growing ecosystem support for RISC-V processor cores, an established and growing software and development tool library, and a growing army of knowledgeable programmers who are familiar with the architecture, having likely learned about the RISC-V architecture in college. In addition, the switch means that Mobileye’s SoCs are no longer chained to a proprietary microprocessor architecture available from a single supplier. The company now finds itself awash in a rising sea of RISC-V processor core vendors. In fact, that’s one of the biggest advantages that RISC-V offers: core vendor choice.

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