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Agile Analog launches first complete RISC-V analog IP subsystem

By June 5, 2023June 16th, 2023No Comments

Agile Analog has brought together its customisable IP blocks to create the first complete analog IP subsystem for battery-powered RISC-V chips.

The initial subsystem includes all the analog IP required for a typical battery powered IoT system. These include the power management unit (PMU), a sleep management unit (SMU), and data converters detailed by eeNews Europe in April. The process agnostic, customisable and digitally wrapped analog IP subsystem will pair with a RISC-V core to form a complete design for digital chip developers.

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