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Complete RISC-V analog IP subsystem targets IoT | Jean-Pierre Joosting, EE News Europe

By June 5, 2023June 12th, 2023No Comments

Agile Analog is offering the first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona. The initial subsystem includes all the analog IP required for a typical battery powered IoT system, including a power management unit (PMU), a sleep management unit (SMU), and data converters. This unique, process agnostic, customizable and digitally wrapped analog IP subsystem will help solve many of the issues that System on Chip (SoC) designers currently encounter, as it pairs with a RISC-V core to form a complete solution.

Chris Morrison, Director of Product Marketing at Agile Analog, explains,“The RISC-V architecture is enabling a surge of new SoC product developments, and the demand for more accessible and configurable IP is increasing. One of the major challenges that digital chip designers face is in integrating the analog circuitry to support their SoC designs.”

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